1. Field of the Invention
The present invention relates to a sample hold circuit incorporating a switch of a low distortion capable of reducing a distortion of an output signal by changing an ON resistance of the switch to which an analogue input signal is supplied.
2. Description of the Related Art
FIG. 1 is a circuit diagram showing a configuration of a conventional sample hold circuit. In FIG. 1, the reference number 121 designates a MOS transistor switch, and 122 denotes a sample hold processing section. Thus, the conventional sample hold circuit comprises the MOS transistor 121 for sampling an analogue input signal and the sample processing section 122 for sampling the analogue input signal.
Next, a description will be given of the operation of the conventional sample hold circuit shown in GIG.1.
When the conventional sample hold circuit performs sampling of analogue input signals, the ON resistance R of the MOS transistor switch 121 is proportional to the inverted value of a value obtained by subtracting a voltage difference V.sub.GS between a gate terminal G and the source terminal S of the MOS transistor switch 121 from a value of a threshold voltage V.sub.th of the MOS transistor switch 121. For example, the ON resistance can be expressed by the following equation (1): EQU R=1/.beta.(V.sub.GS -V.sub.th) (1)
where .beta.=.mu..sub.0 W/L, .mu..sub.0 is a gain coefficient, W is a channel width, and L is a channel length.
Accordingly, when the conventional sample hold circuit shown in FIG. 1 samples the analogue input signal through the MOS transistor switch 121, the ON resistance value R of the switch is changed according to the voltage of the analogue input signal. Thereby, the output signal held by and output from the MOS transistor switch 121 includes a signal distortion. This signal distortion generated in the conventional sample hold circuit shown in FIG. 1 introduces a drawback that a signal to noise ratio (S/N ratio) is decreased. The S/N ratio is used as an index of the performance of the A/D converter.
In order to eliminate the signal distortion in the output wave from the MOS transistor switch 121 in the conventional sample hold circuit, the following methods are used.
In a first method, a voltage amplitude Vdd of the clock signal CLK to be supplied to the gate terminal G of the MOS transistor switch 121 is set to a large value. Thereby, the dependency of the ON resistance R of the MOS transistor switch 121 on the input voltage of the analogue input signal is proportional to the inverted value of the voltage amplitude squared VDD.sup.2 of the clock signal CLK. This conventional method can decrease the signal distortion of the output wave of the sample hold circuit.
In a second method, a circuit to overlap the input signal to the clock signal CLK to be supplied to the gate terminal G of the MOS transistor switch 121 is introduced so that a voltage difference between the gate terminal G and the source terminal S of the MOS transistor switch 121 becomes a constant value.
In a third method, a size of the MOS transistor switch 121 is increased. This method means that the value .beta. in the above equation (1) is increased. Because the dependency of the ON resistance T of the MOS transistor switch on the input voltage of the analogue input signal is inversely proportional to the value .beta., the distortion of the output signal is decreased.
In a fourth method, a value V.sub.th of the threshold voltage of the MOS transistor switch is decreased.
In conventional sample hold circuits, one of the above methods, or a combination of the above first to fourth methods are used in order to decrease the distortion of the output wave from the MOS transistor switch incorporated in the sample hold circuit.
Because the conventional sample hold circuit has the above configuration, according to the recent improvements of MOS transistors in size, integration, and performance, it is required to use the voltage of 3 V in 0.5 .mu.m process in order to keep a withstanding voltage at a gate terminal, the voltage of approximately 3V in 0.35 .mu.m process, and the voltage of 2V or less in 0.2 .mu.m process. This means the voltage of the power source tends to shift a lower voltage. In this case, the distortion of the output signal generated by the ON resistance of the MOS transistor switch in the sample hold circuit becomes a large factor. Thereby, the distortion of the output signal greatly limits an allowed range of the input voltage in the A/D converter. In the tendency toward a low voltage of the power source, the conventional first and second methods described above can not eliminate the adverse effect by the distortion of the output wave from the MOS transistor switch in the sample hold circuit while keeping the withstanding voltage at the gate terminal. In addition, in the low voltage of the power source, the third and fourth conventional methods described above can not eliminate completely the adverse effect by the distortion of the output wave from the MOS transistor switch in the conventional sample hold circuit when this MOS transistor switch enters ON.